This invention relates to the manufacture of thin-film field effect transistors and, in particular, concerns a process for patterning the source-drain contacts in such transistors.
In some types of imaging and display devices, a thin-film field-effect transistor (TFT) is associated with each pixel. The TFT must be small for several reasons. One, it consumes space within the pixel, which would otherwise be devoted to light collection or light control. Two, the TFT must be small because the pixels themselves are small; over one million pixels may be constructed on a plate measuring 8.times.8 inches. Three, the TFT must be small to minimize (a) the total gate capacitance, (b) the gate-to-source capacitance, and (c) the gate-to-drain capacitance.
The total gate capacitance should be small in order to reduce the total capacitance of the address line (i.e., scan line) which controls a row of TFTs in the imaging or display device. The charging time of this address line is controlled by the product of the line resistance and line capacitance. The total gate capacitance is added to the line capacitance in determining the address line charging time.
The gate-to-drain and source-to-gate capacitances should be small to minimize the coupling capacitance between the input address line, which is connected to the gate, and the imaging or display element connected to the source or drain.